About

I will be joining the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities, as an Assistant Professor in Spring 2024. My research interest resides in the intersection between Domain-Specific Acceleration Chip and Computer Architecture. In particular, my Ph.D. research centers around enabling AI-powered intelligent functionalities on resource-constrained edge devices, particularly highlighting a holistic solution from efficient architectures (SmartExchange ISCA'20), to chips (i-FlatCam VLSI'22, e-G2C VLSI'22), and to integrated systems (i-FlatCam VLSI'22, EyeCoD ISCA'22 (Selected as IEEE Micro Top Picks'23)) and advocating the design insight of marrying algorithm-hardware co-design techniques with application-level opportunities. I also developed an analytical performance/cost model for DNN accelerators (DNN-Chip Predictor ICASSP'20) to facilitate fast design space exploration and optimization before actual chip implementation.

I am now a postdoctoral research at the EIC lab of Georgia Institute of Technology, after obtaining my Ph.D. degree (Dec. 2022) from Rice University. Both my postdoctoral and Ph.D. study are under the supervision of Prof. Yingyan Lin. Before joining Rice, I was a Ph.D. student in Prof. Yuan Xie's group for one year and worked on DNN accelerator security and NoC chiplet design. I received my MS and BS degrees from Fudan University, China. During my MS. study, I was advised by Prof. Zhiliang Hong and was working on a digital radio-frequency transmitter.